The online compiler allows you to flatten and/or obfuscate a verilog module. All major transformations of the Veriparse tools will be applied in order to obtain an unique module flattened without any remaining parameters. All information statically known will be used to elaborate the design.
You must put all necessary modules in the "Verilog Source" editor; if a module is missing, it will not be flattened during the process and all corresponding instances will be considered as black boxes.
As multiple modules can be written in the "Verilog Source" editor, it is mandatory to indicate which module you want to flatten by entering the top name in the form provided for this purpose.
If you want to preserve a parameter in the generated output, you must remove the default value.